1. Field of the Invention
The present invention relates to a-terminal equipment capable of controlling an address space of a bus connecting a plurality of hardware modules, such as for allocating and clearing portions of the address space.
2. Description of the Related Art
Specific addresses are allocated to a plurality of memories by using modifier registers, according to a conventional method described in Japanese Patent Laid-open Publication JP-A-58-195263.
There is also described in Japanese Patent Laid-open Publication JP-A-63-62062 a method of allocating an address space using a switch of a hardware module when mounting it on terminal equipment.
The former conventional technique assigns a specific address space to a memory by setting a modifier register. This technique does not allow a CPU to recognize the capacity of a memory to which a specific address space has been allocated by the modifier register, i.e., the capacity of the memory occupying the address space. In order to allocate address spaces to hardware modules, mainly I/O adapters, without creating overlapping address spaces and idle address spaces, it is necessary to set a fixed capacity for each memory or the like having an address space allocated by the modifier register.
The conventional technique in JP-A-58-195263 aims at allocating address spaces to memories. It does not allow a CPU to recognize the type of each hardware module having an address space allocated by modifier registers.
With the former conventional technique, therefore, it is not possible to efficiently allocate address spaces to hardware modules, such as I/O adapters, of different types having different address space capacities.
The latter conventional technique does not allow a CPU to recognize the type and address space capacity of each hardware module, so that an operator has to check the address space capacity of the module, and to allocate an address space by using a switch when mounting the module on the terminal equipment when increasing the number of applications. Therefore, the operator is necessarily required to be an expert. Furthermore, there is a restriction that the total address spaces of hardware, such as memories and I/O adapters, should not exceed the total address spaces of a bus.